This module looks at the methodology of designing and implementing large digital systems. Students taking this module will learn how to design reliable digital systems using synchronous design techniques, will learn how to design digital systems which are easily testable and will be able to use a range of software tools which synthesize digital systems using VHDL.
This module appears in the following module collections.
Contact hours 36 comprising of:
Lectures 30 hours
Examples classes 2 hours
Workshops 4 hours
Method of assessment
See the library reading list for this module (Canterbury)
Ability to design reliable digital systems using synchronous design techniques
Ability to design digital systems which are easily testable
Ability to use a range of software tools which synthesize digital systems from VHDL
Understanding of the major engineering problems associated with building high speed digital systems and how they are solved
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Credit level 6. Higher level module usually taken in Stage 3 of an undergraduate degree.
- ECTS credits are recognised throughout the EU and allow you to transfer credit easily from one university to another.
- The named convenor is the convenor for the current academic session.
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