This module is not currently running in 2024 to 2025.
This module will cover the fundamental concepts of digital circuit design using CMOS technology. It begins with an overview of CMOS technology and introduces the simple and extended circuit models for NMOS and CMOS transistor devices. The module will cover transistor level design of logic gates (both combinatorial and sequential) at the device and layout level. It will include memory design (ROM, SRAM and DRAM) and memory decode logic. Static and dynamic clocking methods will be described including examples of 1-phase, 2-phase, 4-phase clocking and Domino and NORA logic techniques. The course will also cover alternative low-power logic families such as DCVS and Adiabatic Logic and discuss the implications of modern methods such as the use near- and sub-threshold logic on circuit design. Chip level design methodologies such as full-custom, semi-custom and standard cell will be explored. The course will use appropriate CAD tools (Cadence®, Synopsys®, Tanner®) and modern fabrication technologies (down to 65 nm) that are common in the design of CMOS integrated circuits to illustrate the range of techniques and methods described in the lectures. Students will use knowledge gained in lectures and workshops to develop their own IC designs in the laboratories.
Total contact hours: 90
Private study hours: 60
Total study hours: 150
Coursework (40%)
Examination (60%)
See the library reading list for this module (Canterbury)
1) A detailed understanding of the operation of the MOS transistor and an ability to design digital circuits using CMOS technology that operate within a specified range of voltages, currents and temperatures when fabricated on an integrated circuit. An ability to use CAD tools to model and verify the operation of logic CMOS circuits.
2) A detailed practical understanding of CMOS design rules and the impact of circuit layout on circuit performance. An ability to use CAD tools to build and verify the operation of basic CMOS logic circuits. An appreciation of different circuit design techniques including full- and semi-custom methods and the use of CAD tools and their conflicting impact on device cost and designer productivity.
3) A detailed understanding of basic combinatorial and sequential logic circuits and an appreciation of the impact of different clocking strategies on circuit design and performance.
4) An understanding of CMOS memory design including ROM, PLA, Static and Dynamic RAMs and memory addressing techniques including row & column decoders. An appreciation of other volatile and non-volatile memory types such as EPROM, EEPROM, FRAM and MRAM and their current and future impact on modern fabrication technologies.
5) An understanding of Data Path components including Adders, ALUs, Registers and Multiplier Design. The ability to design, build and verify the operation a simple data-path circuit using modern CAD tools.
6) An appreciation of digital fault mechanisms and formal test strategies for circuits and chips. An understanding of formal methods for Automatic Test Pattern Generation (ATPG). A detailed understanding of the IEEE1149.1 Boundary Scan (or JTAG) Standard and its derivatives.
7) The ability to design and build a digital circuit from a system specification and evaluate its performance.
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