This module is not currently running in 2024 to 2025.
Lecture Syllabus
RECONFIGURABLE SYSTEMS
Introduction to reconfigurable systems. PLDs, PLAs, FPGAs. Fine grain architectures, Coarse grain architectures, Heterogeneous device Architectures. Mesh architectures. Case studies. Modelling of systems on reconfigurable architectures. Implementing processor cores on FPGA fabrics. Place and Route algorithms for FPGAs. Configuration of FPGA's. Run-time configuration, partial configuration, dynamic reconfiguration. Partitioning systems onto a reconfigurable fabric. Synthesis tools. Timing issues. Verification and Test strategies.
Hardware/Software design issues. Economic issues.
INTRODUCTION TO HDLs
This short lecture course will revise the basic principles of designing digital systems using a Hardware Description Language. VHDL will be used to illustrate a typical HDL (but this may change to Verilog, Handel-C o r SystemC in future). The lectures will revise the architectural aspects of VHDL: entity, architecture, process, package, types, operators, libraries, hierarchy, test benches and synthesisable VHDL before introducing embedded processing elements in FPGAs. The Xilinx EDK will be used to introduce the MicroBlaze and PicoBlaze processor cores as examples. The lectures will be accompanied by 10 hours of design exercises in the laboratory.
COMPUTER ARCHITECTURES
Basic architecture models. Data Types and operations, the CPU, instruction sets, memory, addressing modes. Subroutines, stacks and heaps. Performance Metrics. Improving Performance. Von-Neuman architecture, Harvard Architecture, RISC, CISC, VLIW, SIMD, MIMD and DSP architectures. Pipelining, Cache memories. Interfacing to the real world. I/O. Interrupts. Embedded processors. Multiprocessing. Advanced Architectures. Dynamic instruction sets. Application Specific Signal Processing (ASSP). Power Issues.
COMPUTER ARITHMETIC
Basic computer arithmetic. Fixed-point and Floating point number representations. The IEEE-754 FP standard. Redundant Number Systems. Residue Number Systems. Methods for Addition and Subtraction.
Fast adder architectures. Multi-operand addition. Multiplication: Multiplier architectures; Constant coefficient multipliers; Distributed arithmetic; LUT methods. Special methods: division, square root, the CORDIC algorithm. High-throughput arithmetic. Low-power arithmetic.
Coursework
COMPUTER ARITHMETIC
One assessed report.
ASSIGNMENTS
WORKSHOP - INTRODUCTION TO HDLs
Four non-assessed workshops.
LABORATORIES
Three assessed laboratories.
56 contact hours comprising:
16 hours of compulsory lectures
24 hours of supervised laboratory work
16 hours of instructor-led workshops
Total Student workload 150 hours.
Only available to students on programmes owned by The School of Engineering and Digital Arts
Examination 65%
Coursework 35%
See the library reading list for this module (Canterbury)
An understanding of basic computer architecture including CISC, RISC and VLIW processors.
An understanding of pipelining and cache techniques for improving performance.
An understanding of other common processing architectures such as SIMD and MIMD.
An understanding of computer arithmetic standards, methods and algorithms.
An understanding of reconfigurable architectures including CPLD, FPGA and coarse-grained devices and how to programme them using VHDL.
An understanding of heterogeneous architectures.
An overview of custom, ASIC, Platform ASIC and SoC technologies.
An ability to compare and contrast the advantages/disadvantages of different architectural solutions.
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