Portrait of Mr Winston Waller

Mr Winston Waller

Senior Lecturer in Electronic Engineering

About

Design for test, analogue and digital VLSI design, medical applications of VLSI and low power voltage circuit design.

Publications

Article

  • Walczowski, L., Dimond, K. and Waller, W. (2000). A digital engineering curriculum for the new millennium. International Journal of Electrical Engineering Education 37:108-117.
    This paper examines the development of a digital engineering curriculum, which closely integrates EDA tools and multimedia courseware into the syllabus. It describes the software that has been integrated, including tools for schematic capture, logic simulation. VLSI design and high-level simulation and highlights the advantages of closely integrating computer-based teaching with conventional lecture-based material.
  • Aziz, S. and Waller, W. (1994). Testing Differential Split-Level CMOS Circuits. IEE Proceedings: Circuits, Devices and Systems [Online] 141:451-456. Available at: http://dx.doi.org/10.1049/ip-cds:19941524.
    The paper addresses the problem of testing differential split-level (DSL) CMOS circuits. The behaviour of DSL circuits under single stuck-at, stuck-on and stuck-open faults is analysed. It is shown that most of these faults in DSL circuits cannot be deterministically tested by logic monitoring. However, the presence of any of these faults results in an increase in the steady state power supply current in the circuit when the fault is sensitised. A testing technique based on differential supply current monitoring to detect these faults in DSL integrated circuits is presented.
  • Walczowski, L., Waller, W. and Wells, E. (1992). Teaching full-custom design skills using chipwise. IEE Proceedings G: Circuits Devices and Systems 139:154-160.
    ChipWise is a VLSI design environment, developed at the University of Kent, which integrates symbolic design tools obtained from industry with design tools for hand craft layout. Since 1989, ChipWise has been used at a number of UK higher-educational institutions for teaching VLSI design skills, and became part of the UK Higher Education ECAD Initiative in 1990. The paper describes the design tools and their use in student design projects at the University of Kent.
  • Walczowski, L., Waller, W. and Wells, E. (1991). Teaching Vlsi Design using Chipwise. International Journal of Electrical Engineering Education 28:271-277.
    Chip Wise is a design system for VLSI circuits developed at the University of Kent, based on tools which originated at several academic institutions and tools obtained from industry. From 1st August, 1990, Chip Wise will be included as a supported package within the software portfolio offered by the U.K. Higher Education ECAD Initiative. This paper describes the design tools and their application in a typical laboratory exercise.
  • Howard, D. et al. (1990). Generation of Ordered Sub-circuits for an Automatic Sizing Program. IEE Proceedings G: Circuits Devices and Systems 7:43-44.
    The design of increasingly complex integrated circuits requires synthesis tools rather than analysis tools. A tool that calculates transistor sizes is useful both to design a new circuit and to move an existing design to another process. The paper describes an algorithm that can be used in such a program to structure an otherwise unstructured array of unsized transistors in a CMOS digital circuit. This structure is related to the functionality of the circuit, so that the sizing model is provided with all the information required. The paper then goes on to discuss how the `subcircuits' were ordered so that they could be sized, taking the necessary factors into account
  • Smith, M. et al. (1990). Automatic Device Sizing for Silicon Compilers. Journal of Semi-custom ICs 7:24-28.
  • Walczowski, L., Waller, W. and Wells, E. (1990). ChipWise - a user-friendly VLSI design environment. Journal of Semi-custom ICs 7:43-44.
  • Waller, W. et al. (1989). Student Full Custom Design. International Journal of Electrical Engineering Education 26:113-120.

Book section

  • Waller, W. et al. (1989). Student Full Custom Design. in: Electronic Computer Aided Design. Manchester University Press.

Conference or workshop item

  • Walczowski, L. and Waller, W. (1999). Java servlet technology for analogue module generation. in: Proceedings of 1999 IEEE International Conference on Electronics, Circuits, and Systems. pp. 1717-1720. Available at: http://dx.doi.org/10.1109/ICECS.1999.814507.
    A World Wide Web (WWW) based client/server system has been developed which uses Java servlet technology. The system allows a server-side, process-independent layout generator servlet to generate active messages, which create design rule correct geometry of analogue components such as resistors, capacitors and transistors within a design system on the local workstation. This combination of server based servlets and active messages is a very powerful technique for developing remote applications which run in cooperation with a local design system, leading to real increases in system availability, functionality and performance
  • Nalbantis, D., Walczowski, L. and Waller, W. (1998). Multiple server WWW-based synthesis of VLSI circuits. in: Proceedings of 1998 IEEE International Conference on Electronics, Circuits, and Systems. pp. 537-540. Available at: http://dx.doi.org/10.1109/ICECS.1998.813379.
    A three-tier client/server system for the synthesis of VLSI circuits has been developed. The design system uses the World Wide Web as a backbone communications medium, whilst the sub-components of the synthesis applications are organised as servers, accessed through client/server communications between a tool server and thin client applets. This paper describes the architecture of the system, and in particular examines the use of multi-threading and multiple servers for improving system performance
  • Nalbantis, D., Walczowski, L. and Waller, W. (1998). Client/Server Architectures for WWW-based Analogue VLSI Synthesis. in: 5th European Concurrent Engineering Conference. pp. 165-168.
  • Walczowski, L., Dimond, K. and Waller, W. (1998). A digital engineering curriculum with integrated, Windows-based EDA tools. in: 1998 IEEE International Conference on Electronics, Circuits, and Systems. pp. 425-428. Available at: http://dx.doi.org/10.1109/ICECS.1998.814022.
    The move to the Windows NT operating system by the University Computing Service, was an excellent opportunity for the Electronic Engineering Department at Kent to develop a new digital engineering curriculum, which closely integrated EDA tools and multi-media courseware into the syllabus. This paper examines the development of the curriculum and describes the software that has been integrated including tools for schematic capture, logic simulation, VLSI design and high-level simulation. The advantages of closely integrating computer based teaching with conventional lecture based material are described
  • Shi, K. et al. (1996). Object Technology For Analogue VLSI Design. in: 3rd International Conference on Concurrent Engineering & Engineering & Electronic Design Automation. pp. 178-181.
  • Walczowski, L., Waller, W. and Nalbantis, D. (1996). VLSI design training with the help of the World Wide Web. in: IEE Colloquium on Learning at a distance: developments in media technologies. pp. 8-8. Available at: http://dx.doi.org/10.1049/ic:19960881.
  • Waller, W., Walczowski, L. and Nalbantis, D. (1996). A new bipolar op-amp IC synthesis approach. in: Zhang, Q., Tang, T. -A. and Yu, H. eds. 2nd International Conference on ASIC. Shanghai Scientific & Technical Literature Publ, pp. 57-60.
    Bipolar op-amp IC modules with a simple circuit structure are difficult to design for a wide range of design specifications, due to strong correlations between transistor parameters. As a result, bipolar op-amps are commonly designed resorting to complicated circuit structures which result in large chip area and high fabrication cost. We have developed a new synthesis approach which can generate bipolar op-amp IC modules for a wide range of design specifications with a simple structure. The approach incorporates two new methods which we have developed to predict Miller capacitance and to calculate transistor transconductance during transistor sizing. Differing from conventional methods, our methods consider the effect of device parasitics during the synthesis and hence are accurate. The approach has been implemented in our bipolar op-amp IC Synthesis package.
  • Walczowski, L., Waller, W. and Nalbantis, D. (1996). Rapid layout synthesis for analog VLSI. in: 3rd IEEE International Conference on Electronics, Circuits, and Systems (ICECS 96). IEEE, pp. 378-381.
    A technology independent synthesis system which rapidly generates the layout of analog VLSI circuits has been developed. Based on a specification of a circuit's required performance and the target process, design rule correct layout is generated. The complete system has been tested by synthesizing op-amps in the CMOS and bipolar domains. Comparison of the specification with results of simulating the circuit extracted from the synthesized layout, show that the system is accurate to within a few per cent for most parameters.
  • Walczowski, L. and Waller, W. (1996). A World Wide Web based System for VLSI Design Training. in: European Workshop on Microelectronics Education. pp. 39-42.
  • Nalbantis, D., Walczowski, L. and Waller, W. (1996). O-2 ADL: An object-oriented analog VLSI design language. in: Zhang, Q., Tang, T. -A. and Yu, H. eds. 2nd International Conference on ASIC. Shanghai Scientific & Technical Literature Publ, pp. 27-30.
    Object technology can be applied to analog VLSI design to exploit circuit compositional hierarchy, design process hierarchy and design module reuse. Conventional Object-Oriented programming languages are not suitable for such application due to the difficulties in describing VLSI circuit behaviour, modelling design technology/process hierarchy, implementing class name sharing and dynamically configuring design database. To overcome these difficulties, we have developed an Object-Oriented analog VLSI design language which provides a set of high-level constructs to conveniently describe and design VLSI circuits. A number of new concepts have been introduced in O(2)ADL and a Dynamic-and-Selective Inheritance algorithm has been developed to model the design technology/process, to reduce the size of the design database and to achieve code sharing and reusability.
  • Walczowski, L. et al. (1996). Technology Independent Compilation of Analogue VLSI Circuits. in: IT & CS’ 96, Leeds University.
  • Nalbantis, D. et al. (1996). Analogue IC Layout Synthesis Using Symbolic Floorplans. in: 3rd International Conference on Concurrent Engineering & Electronic Design Automation. pp. 175-177.
  • Waller, W. and Aziz, S. (1994). A C-Testable Parallel Multipler Using Differencial Casecode Voltage Swish (DCVS) Logic. in: Yanagawa, T. and Ivey, P. A. eds. IFIP TC10/WG10.5 International Conference on Very Large Scale Integration (VLSI 93). Elsevier Science Publ B V, pp. 133-142.
    In this paper, a new C-testable design of a parallel multiplier is presented. It is based on the well known modified Booth's algorithm which reduces the number of partial products by a factor of two compared to the straightforward iterative array multiplier. The multiplier is implemented using the highly testable clocked Differential Cascode Voltage Switch (DCVS) logic. It requires only 21 test vectors to detect all detectable single stuck-at, stuck-on and stuck-open faults. Compared to a non-C-testable DCVS design, it requires only 6 extra inputs, 2 extra outputs and a small amount of extra logic which is also self-checking.
  • Walczowski, L. et al. (1993). C.S.L.: An Object Oriented Language for Process Independent V.L.S.I. Design. in: OOPSLA ‘93.
  • Waller, W., Walczowski, L. and Wells, E. (1993). A Fast Track Approach to Teaching Full Custom VLSI Design. in: 4th Eurochip Workshop on VLSI Design.
  • Waller, W. and Walczowski, L. (1991). Consideration in the Selection and Supervision of VLSI Design Projects. in: IEE Colloquium on the EUROCHIP Project.
    VLSI design encompasses a wide range of skills including, at one extreme the specification of a design using a hardware description language such as VHDL and at the other extreme, polygon level layout of high performance analogue circuits. It is not possible to address the entire range in a single project so a sub-range must be chosen. This presentation describes the approach to address this subject, taken at the University of Kent
  • Smith, M. et al. (1991). A method for sizing transistors in CMOS op-amps. in: IEEE International Symposium on Circuits & Systems. pp. 2016-2019. Available at: http://dx.doi.org/10.1109/ISCAS.1991.176061.
    The authors present a method for automatically calculating the size of the transistors and passive components in a CMOS op-amp given the specification and loading of the op-amp. The method is similar to that used in the OASYS program in that it uses no simulation. Like the OASYS method, the authors estimate the sizes and then calculate the parasitics. The parasitics calculated are then used to recalculate the sizes. This process continues until the parasitics change only little. Unlike OASYS, the authors separated the sizing method from the model of the transistor. This means one is able to use any transistor model to size the transistors, and, because the method does not use simulation and so makes less calls of the model equations, the model used can be more complicated than that used for simulation
  • Waller, W., Walczowski, L. and Wells, E. (1991). Techniques for Effective VLSI Design. in: Proceedings of the 1991 International Conference on Concurrent Engineering & Electronic Design Automation. pp. 273-277.
  • Walczowski, L. et al. (1991). Device sizing for silicon compilers using CSL. in: IEEE Custom Integrated Circuits Conference ’91. pp. 22.2/1-22.2/4. Available at: http://dx.doi.org/10.1109/CICC.1991.164063.
    The authors present an overview of a system designed to generate integrated circuits so that they meet their performance specifications. The system is based around CSL (Circuit Specification Language), an object-oriented language designed specifically for the purpose of generating integrated circuits. The usefulness of CSL in calculating the size of transistors in the circuit so that they meet the specification is discussed. This is the task for which CSL was originally designed but it is believed that it will prove capable of handling all stages of silicon compilation
  • Waller, W. et al. (1991). ODIN: A Software System for Synthesizing CMOS Op-amps. in: International Conference on Concurrent Engineering & Electronic Design Automation. pp. 74-79.
  • Smith, M. et al. (1990). Specification Driven Synthesis of CMOS Op-amps. in: IEE Colloquium on Analogue VLSI. pp. 3/1-3/4. Available at: http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=190117.
    Describes a suite of programs that calculate the sizes of the transistors in CMOS operational amplifiers for a given performance specification. The aim is to reduce the role of simulation to that of a simple check to characterize the amplifier. To make this possible the authors have developed ways to introduce parasitic components into the synthesis. The sizing programs make an initial estimate of sizes and then use the parasitics associated with the transistors to make a more accurate calculation of the sizes. In this paper the authors describe the technique for the Unity Gain Bandwidth (UGB) and Phase Margin. The average error in these parameters is 4% over a range of frequencies from 1 MHz to 10 MHz
  • Howard, D. et al. (1990). CSL: A Language for Process Independent VLSI Design,. in: IEE Colloquium on Applications and Experience of Object-Oriented Design. pp. 5/1-5/3.

Book

  • Walczowski, L. et al. (1997). Analogue layout generation by World Wide Web server-based agents. [Online]. USA: I E E E, Computer Soc Press. Available at: http://bookshop.blackwell.co.uk/jsp/id/Proceedings/9780818677861.
    A World Wide Web (WWW) based client/sewer system has been developed which allows server-side process independent layout generators to generate the design rule correct geometry of analogue components such as resistors, capacitors and transistors for a design system running on a local workstation. The complete system is based on the bidirectional interface between a WWW browser and a VLSI design system, with layout generators running remotely on a WWW server.